Articles from JEDEC

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4). SPHBM4 devices are similar to the HBM4 devices commonly used in artificial intelligence accelerators, using the same DRAM dies on a new interface base die which can be mounted on standard organic substrates. In contrast, HBM4 is typically mounted on silicon substrates.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, has published the annual release of its JESD400-5D DDR5 Serial Presence Detect (SPD) Contents standard. This latest version 1.4 adds support for memory modules executing up to DDR5-9200 speeds, codes for the new Small Outline Compression Attached Memory Module (SOCAMM2) and expands error logging information for Multiplexed Rank Dual In-Line Memory Modules (MRDIMMs). For free download visit the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD220G: Universal Flash Storage 4.1. In addition, an update to the complementary JESD223F UFS Host Controller Interface (UFSHCI) version 4.1 standard has also been published. Developed for mobile applications and computing systems requiring high performance with low power consumption, UFS 4.1 offers faster data access and improved performance over the earlier version of the standard while maintaining hardware compatibility to UFS 4.0. Both standards are available for download from the JEDEC website.

JEDEC® Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD230G: NAND Flash Interface Interoperability Standard. JESD230G introduces speeds of up to 4800 MT/s, as compared to 400 MT/s in the first version of JESD230 published in 2011. Also, JESD230G adds a separate Command/Address Bus Protocol (SCA), delivering enhanced throughput and efficiency by allowing hosts and NAND devices to take maximum advantage of the latest interface speeds. JESD230G is available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of PS-007A LPDDR5 CAMM2 Connector Performance Standard. The connector, referred to as "LP5CAMM2," is designed to offer a standardized modular LPDDR5 solution with ecosystem support, unlike the traditional LPDDR5 memory-down approach. Developed by JEDEC’s JC-11 Committee for Mechanical Standardization, PS-007A is available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced upcoming raw card designs currently in development in JEDEC’s JC-45 Committee for DRAM Modules in collaboration with the JC-40 and JC-42 Committees. These raw card memory device standards are intended for use in client computing applications such as laptops and desktops and will be supported by related appendix specifications. The forthcoming raw cards will also complement two DDR5 Clock Driver standards published earlier this year: JESD323: DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Specification and JESD324: DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Common Specification.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of two new standards supporting Compute Express Link® (CXL®) technology. These additions complete a comprehensive family of four standards that provide the industry with unparalleled flexibility to develop a wide range of CXL memory products. All four standards are available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JEP200: Test Methods for Switching Energy Loss Associated with Output Capacitance Hysteresis in Semiconductor Power Devices. Developed jointly by JEDEC’s JC-70.1 Gallium Nitride and JC-70.2 Silicon Carbide Subcommittees, JEP200 is available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of the JESD406-5 LPDDR5/5X Serial Presence Detect (SPD) Contents V1.0, consistent with the updated contents of JESD401-5B DDR5 DIMM Label and JESD318 DDR5/LPDDR5 Compression Attached Memory Module (CAMM2) Common Standard. To download these and other published JEDEC documents, visit the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced that it is hosting an Automotive Electronics Forum on September 19, 2024 in San Jose, CA. There is no charge to attend, but advance registration is required and space is limited. For more information and registration, visit the JEDEC website.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD405-1B JEDEC® Memory Module Label – for Compute Express Link® (CXL®) V1.1. JESD405-1B joins JESD317A JEDEC® Memory Module Reference Base Standard – for Compute Express Link® (CXL®) V1.0, first introduced in March 2023, in defining the function and configuration of memory modules that support CXL specifications, as well as the standardized content for labels for these modules. JESD405-1B and JESD317A were developed in coordination with the Compute Express Link standards organization. Both standards are available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of a new release of the JEP30 PartModel Guidelines, including reference documents and related XML Schema files. JEP30 and its supporting documents and resources are available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced publication of the JESD79-5C DDR5 SDRAM standard. This important update to the JEDEC DDR5 SDRAM standard includes features designed to improve reliability and security and enhance performance in a wide range of applications from high-performance servers to emerging technologies such as AI and machine learning. JESD79-5C is now available for download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, is pleased to announce the publication of JESD239 Graphics Double Data Rate (GDDR7) SGRAM. This groundbreaking new memory standard is available for free download from the JEDEC website. JESD239 GDDR7 offers double the bandwidth over GDDR6, reaching up to 192 GB/s per device, and is poised to meet the escalating demand for more memory bandwidth in graphics, gaming, compute, networking and AI applications.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD318: Compression Attached Memory Module (CAMM2) Common Standard. This groundbreaking standard defines the electrical and mechanical requirements for both Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LPDDR5/5X SDRAM CAMM2s) in a single, comprehensive document. JESD318 CAMM2 is available for download from the JEDEC website.

In an extraordinary leap forward for the chiplet industry, the groundbreaking collaboration between the Open Compute Project Foundation (OCP) and JEDEC is set to usher in a new era of innovation. By merging the capabilities and open standards of OCP’s Chiplet Data Extensible Markup Language (CDXML) and JEDEC’s JEP30 PartModel Guidelines, this partnership, initiated in late 2022, promises to revolutionize chiplet design, manufacturing and integration. The result will be a unified structure that supports both chiplets and general electronic parts within the overarching purview of JEDEC.

The JEDEC Board of Directors presented its prestigious 2023 Distinguished Executive Leadership Award to AMD Chair and CEO, Dr. Lisa T. Su, in a ceremony held at AMD's offices in San Jose, CA. This award stands as JEDEC’s highest honor and recognizes the most distinguished senior executives in the electronics industry who promote and support the advancement of JEDEC standards.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced the publication of JESD317: Compute Express Link (CXL™) Memory Module Base Standard, known as “CMM”. JESD317 CMM defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features as reference for specific target implementations of CXL™-attached memory modules, and is available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced significant updates to the JEP30 PartModel Guidelines, including all reference documents and related XML Schema files. JEP30 and its constituent documents are available for free download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced an expansion of its CAMM standardization activity to include stackable CAMMs and support of LPDDR5.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announces the formation of the JC-42.9 Automotive Steering Subcommittee responsible for investigating memory technologies and recommending solutions pertaining to automotive applications. Following the Board of Directors’ approval earlier this month, the new subcommittee will hold its first meeting in Seattle, WA, during the week of March 6th, 2023.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, announces the publication of JEP194: Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs, JEP195: Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion, and JEP192: Guidelines for Gate Charge (QG) Test Method for SiC MOSFET. The publications were developed by JEDEC’s JC-70.2 Silicon Carbide Subcommittee and are available for free download from the JEDEC website.

Today, the Open Compute Project Foundation (OCP), the nonprofit organization bringing hyperscale innovations to all, and JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, announce a new collaboration to establish a framework for the transfer of technology captured in an OCP-approved specification to JEDEC for inclusion in one of its standards. This alliance brings together members from both the OCP and JEDEC communities to share efforts in developing and maintaining global standards needed to advance the electronics industry.

JEDEC Solid State Technology Association, the global leader in standards development for the microelectronics industry, today announced the publication of JESD312 Automotive Solid State Drive (SSD) Device Standard V1.0. JESD312 defines the packaging, protocol, environmental requirements, and electrical interface for an SSD targeted at use in automotive and similar ruggedized applications. JESD312 is available for download from the JEDEC website.

JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced that it is hosting a Server/Cloud Computing/Edge Forum, a Memory Tutorial introductory class, and an in-depth, two-day technical workshop focused its DDR5 standard in Santa Clara, CA from May 23-26, 2022. Space is limited and for best rates, register now on the JEDEC website.

The JEDEC Board of Directors passed a resolution yesterday at its November board meeting naming Jung-Bae Lee, Ph.D. and president of the Memory Business at Samsung Electronics, as the recipient of its Distinguished Executive Leadership Award for 2022. The resolution passed unanimously.